1. Field of the Invention
The present invention relates to a semiconductor transistor, and particularly, to an ultra-short channel metal-oxide-semiconductor field effect transistor (MOSFET) with an inverse-T gate lightly-doped drain (ITLDD) structure.
2. Description of the Prior Art
Metal-oxide-semiconductor (MOS) devices with ultra-short (less than 0.1 .mu.m) channel are required for high frequency operation, for example, in a high-speed ring oscillator. The major constrains for 0.1 .mu.m (or less) gate length metal-oxide-semiconductor field effect transistor (MOSFET) device used, for example, in giga-bit dynamic random access memories (DRAMs) are short channel effect and hot carrier reliability problems. To solve these problem, some process techniques such as ultrashallow junction and ultra-thin gate oxide are used. For example, a device design window of process conditions such as oxide thickness, punch-through doses, and lightly-doped drain (LDD) doses is disclosed in Hyunsang Hwang et al., "Performance and Reliability Optimization of Ultra Short Channel CMOS Device for Giga-bit DRAM Applications," IEEE IEDM Tech. Dig., pages 435-438 (1995) which is hereby incorporated by reference.
However, it becomes difficult to define a gate length below 0.1 .mu.m due to some practical limitations, such as the resolution, under current optical photolithography technique. In order to circumscribe this situation, a resistor-thinning process based on an isotropic plasma resist ashing technique is applied in forming short channel MOSFETs with the gate length below 0.1 .mu.m as disclosed in Mizuki Ono et al., "Sub-50 nm Gate Length N-MOSFETs with 10 nm Phosphorus Source and Drain Junctions," IEEE IEDM Tech. Dig., pages 119-122 (1993) which is also hereby incorporated by reference.
When the MOSFET devices are operated at a low supply voltage, the parasitic resistance effect due to the lightly-doped drain (LDD) structure should be reduced to maintain their performance. Further, the peak field location under the gate should be properly controlled, so that the hot carrier effect germane to the LDD structure can be improved. An inverse-T lightly-doped drain (ITLDD) transistor structure is disclosed in Tiao-Yuan Huang et al., "A New LDD Transistor with Inverse-T Gate Structure," IEEE Electronic Device Letters, VOL. EDL-8. No. 4, pages 151-153 (1987) which is hereby incorporated by reference. Although this ITLDD structure can alleviate hot carrier effect, its process is still not suitable for high-density or high-speed circuit application, in which fabrication of ultra-short channel devices with gate length less than 0.1 .mu.m is required.